In this series of tutorial I planned to explain the Zynq 7000 architecture in details. The series is divided into three parts:
- Firstly, the peripheral interfaces of processor and FPGA will be explained and implemented in vivado.
- Secondly, AXI interfaces (AXI4, AXI-Stream, and AXI-lite) will be demonstrated.
- Lastly, Advance features of Zynq 7000 architecture will be realized e.g performance measurements of DMA , OCM, DDR etc.
I, however, find it better to briefly explain the basic concepts that shall be used later in this series.
hybrid hardware architecture
Nowadays hybrid hardware architecture (HHA) is increasingly being used in embedded systems (ES). A typical ES has processor, memory unit and inputs/outputs (IOs). Processor is the brain that control the entire ES. Memory supports the processor by holding data temporarily or permanently. IOs are used to interact with external world. Sometimes single processor is not enough to meet all requirements. Therefore some other devices such as FPGA or application specific integrated circuit (ASIC) are embedded with processor to meet the given requirements. This kind of architecture is called hybrid architecture. The typical example of HHA is shown in the following Figure. A typical example of this architecture can be seen in ZYNQ 7000 series.
System on Chip
In System on Chip (SoC) the electronic components are integrated on a single chip. The components can be analog, digital or mixed signals. Xilinx has introduced a new realm called All Programmable SOC (AP-SoC). In AP-SOC software programmability of a processor and the hardware programmability of an FPGA are integrated in a single chip. A typical example of this architecture can be seen in ZYNQ 7000 series.
In the following series of tutorial I will use ZEDBOARD which is an evaluation board with ZYNQ 7000 AP-SOC together many integrated peripherals.
How an FPGA Works
Before diving into ZEDBOARD, reader should have some basics about how an FPGA works. Assuming reader already knows about processor, I have given a general overview of an FPGA in the following few paragraphs. In this module, an effort is made to explain the general architecture of a FPGA. A top down approach (from general to specific) is employed in this tutorial.
“A picture is worth a thousand words” as stated by Fred, therefore we added as many pictures as possible to explain the concepts in easiest way. Following Figure shows the simplest form of an FPGA architecture. It is worth to note that real FPGA are much more complex than this. However, more or less, basic components remains same in all FPGA architectures. An FPGA has mainly three parts: CLB (Configurable Logic Block), routing channel, and IO (Input Output) Bank.
CLB are reprogrammable blocks used to implement any kind of logic. Routing channel enables different CLB to communicate with each other and IO bank connect the FPGA with the outer world. New FPGAs have more components like DSP block, but these components are not discussed in this tutorial. Lets goes a bit further to FPGA architecture. Each CLB consists of more than one Slices. Group of LUTs(Look Up Table) and flip-flops constitutes Slices. The Figure ,given below, illustrates the relationship between CLBs and LUTs.
LUTs are basically RAMs. Any kind of logic can be implemented by exploiting LUT. Let’s explain this concept by an example. For example, if we want to implement OR gate the contents of the RAM would be like this.
The LUT2 illustrated in following figure outputs based on address_index.
To make long story short, nny kind of complex logic can be implemented by exploiting the LUTs. Of course, more the complex architecture is, more the required LUTs will be.
In the next lecture, The Zynq-7000 family architecture which is based on the All Programmable SoC architecture will be demonstrated. Furthermore, complete plan about when and which part of the AP SoC will be demonstrated. It is worth to note that I will use Zedboard (an evaluation board based on Zynq-7000 architecture) will be used throughout the lectures.