Part 1: Implementation of GPIO via MIO and EMIO in All Programmable SoC (AP SoC) Zynq 7000

Abstract: The tutorial provides a brief overview of available input/output peripherals (IOPs) and their relation with multiplexed input/output (MIO) and extended MIO (EMIO) in Zynq 7000. After that, a comprehensive detail of general purpose input/output (GPIO), which is one of the available IOPs in Zynq 7000, and its programming via MIO and EMIO is explained. Lastly, the GPIOs are implemented by making use of Vivado and Zedboard as a software and hardware platform respectively.

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Detailed explanation of AP-SoC Zynq 7000 Architecture

Zynq 7000 AP SoC ,as shown in Figure given below, mainly consists of two parts: Processor System(PS), Programmable Logic(PL). PS literally employs to implement software functions of a hybrid system while hardware related functions are realized in PL. The PS part in Zynq 7000 is further composed of Application Processor Unit (APU), Memory interfaces, Central interconnects, Input Output Peripherals (IOPs), and Multiplexed IO (MIO). APU is the central part of the PS which controls and regulates all parts of PS.APU can have either single CPU or dual CPU. Two independent L1 D cache and I cache are, respectively, employed for data and instructions in each CPU. Snoop Control Unit (SCU) are exploited to maintain the coherency between L1 caches of both processor. Coherency ensures that caches in the respective CPU have updated data. L2 caches further act as bridge between L1 cache and DDR ram. DDR ram are relatively bigger memory (e.g. 512MB in Zedboard). Besides L1, L2, and DDR ram, there is 256KB On Chip Memory (OCM) which can be used for the application which requires low latency. Watch Dog Timers (AWDT, SWDT) are utilized to reset the PS when it malfunctions.

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AP SoC (Zynq 7000) Hybrid Hardware Architecture Basics

In this series of tutorial I planned to explain the Zynq 7000 architecture in details. The series is divided into three parts:

  • Firstly,  the peripheral interfaces of processor and FPGA will be explained and implemented in vivado.
  • Secondly, AXI interfaces (AXI4, AXI-Stream, and AXI-lite) will be demonstrated.
  • Lastly, Advance features of Zynq 7000 architecture will be realized e.g performance measurements of DMA , OCM, DDR etc.

I, however, find it better to briefly explain the basic concepts that shall be used later in this series. Read more