Running Petalinux based linux system on Zedboard via jtag and SD card

Summary: This short tutorial demonstrates how to run and test the first petalinux based customized linux system on Zedboard via jtag and SD card.

Implementation: This tutorial is the continuation of the first lecture. It thus assumes that the reader has already created, configured and built a petalinux based customized linux system by using petalinux-create, petalinux-config, and petalinux-build commands, respectively. After building the linux system, it can be run and tested on Zedboard via JTAG. To this end, turn on and set the configuration jumpers of the zedboard into JTAG boot mode (see the figure given below).

Then, run the following command from the project directory of petalinux:

  • petalinux-boot –jtag –prebuilt 3   

The command downloads the newly built linux solution into zedboard. Lastly, connect the serial  port of zedboard with the PC and configure its baud rate to 115200. The serial port allows us to do further actions after the linux system is up.

Second part of the tutorial explains the steps necessary to run the linux system on zedboard via SD card as follows.

  • Generate Boot Image which usually contains a first stage bootloader image, FPGA bitstream (optional) and U-Boot. The syntax of the command used to generate the boot image is following:
    • petalinux-package –boot –fsbl <FSBL image> –fpga <FPGA bitstream> –u-boot
  • Prepare SD card for the linux system
    • Insert and unmount all the partitions of the SD card of size 8 Ghz by using umout command:
      • sudo umount /media/<location of mount>
    • Delete the existing partitions and create two new partitions with the first partition of size 1GHz and remaining size for the other partition.
      • sudo fdisk /dev/<name of the directory>
    • After having two partitions, Format the former by using FAT and the later by using ext4. The syntax of the commands is following
      • mkfs.vfat -F 32 -n BOOT /dev/<first partition>
      • mkfs.ext4 -L rootfs /dev/<second partition>  
  • Copy the the necessary files into first partition of SD card
    • cp images/linux/BOOT.BIN /media/<first partition>
    • cp images/linux/image.ub /media/<first partition>
  • Copy the the necessary files into second partition of SD card
      • cp images/linux/rootfs.cpio /media/<second partion>
  • Insert the SD card into SD card slot of zedboard and Configure it into  SD card boot mode (see figure given below).

Lastly, connect the serial  port of zedboard with the PC and configure its baud rate to 115200. The serial port allows us to do further actions after the linux system is up.

The video given below also explains all the steps needed to run and test first Petalinux based linux solution on Zedboard via jtag and SDcard.

 

 

Installation of Petalinux and running the first Petalinux based linux system on QEMU

Summary: This short tutorial, first, defines the petalinux, board support packages (BSP) and quick emulator (QEMU) used in zynq 7000 linux programming. It, secondly, describes the steps necessary to install petalinux on Ubuntu PC. Finally, an example on how to run and test the petalinux based linux system in QEMU is demonstrated.

1.  Definitions of Petalinux, BSP and QEMU: Petalinux, which is based on the yocto project, is a  Xilinx development toolchain which provides us everything necessary to build, test, customize and deploy an embedded linux system. Furthermore, it is an embedded linux distro maintained by Xilinx and targets Xilinx System on Chip (SoC) designs. It also has an integrated full system quick emulator (QEMU).  Developers can test and verify the customized linux solution on QEMU before deploying it on the actual hardware. Additionally, Xilnix also provides Board Support packages (BSP) for various Xilinx evaluation boards. A BSP describes the various hardware features supported by the corresponding evaluation board. Petalinux uses these BSPs to configure the kernel as per specification defined in them.  

2. Installation of Petalinux: The steps used to install the petalinux on Ubuntu 18.04.4 LTS are summarized as follow:

  • Download the petalinux version of your choice from the link (click here for the link). For example, I am using petalinux v2017.4.
  • Change the access permission of the download files by executing the following command. sudo chmod +x <download path>/petalinux-v2017.4-final-installer.run
  • Petalinux tool requires a number of standard development tools and libraries. For your convenience, I have listed all these dependencies here. sudo apt install tofrodo,  iproute, gawk, gcc, git-core, make, net-tools, ncurses-dev, libncurses5-dev, zlib1g-dev, flex, bison, lib32z1, lib32ncurses5, lib32bz2-1.0, ia32gcc1, lib32stdc++6, libselinux1,  libssl-dev,  libssl1.0-dev.
  •  Change the access permission of the location where you want to install the petalinux with this command. sudo chmod 755 <installing location for petalinux>
  • Run sudo chmod 755 /tmp command to change the access permission of tmp folder.
  • Install the petalinux with the command. <download path>/petalinux-v2017.4-final-installer.run <installing location for petalinux>
  • Run the command source <installing location for petalinux>/settings.sh
  • If you get the WARNING: /bin/sh is not bash! After running this command, please run the following subset of commands.
    • chsh -s /bin/bash.
    • Log out and then run these commands.
    • sudo rm /bin/sh.
    • sudo ln -s /bin/bash /bin/sh.
  • Lastly, upon running echo $PETALINUX command, it will give you the installed path of the petalinux.3. Running the first Petalinux based linux system on Qemu: In this tutorial, Zedboard is chosen as a Xilinx evaluation board. The steps involved in testing first petalinux based linux system on QEMU are listed below:
  • Download the corresponding BSP for Zedboard from Xilinx official website (click here for the link).
  • create a basic project template by using petalinux-create command.  petalinux-create -t project -s <location of BSP>/Avnet-Digilent-ZedBoard-v2016.2-final.bsp
  • The project can be customized by using The petalinux-config command. For our special case, we don’t need to do any customization. Run petalinux-config and select exit.
  • Builds either the entire embedded Linux system or a specified component of the Linux system by using petalinux-build command. for our example, please run petalinux-build.

After petalinux-build command, the linux solution is ready to deploy into hardware. We however first run the solution on QEMU to verify the functionality of the newly built linux system. petalinux-boot –qemu command is used to run the linux system on QEMU. after running the petalinux-boot –qemu –kernel, you need to login with following credential: username: root, password: root. The video given below explains all the steps needed to install and run first Petalinux based linux solution on QEMU.

Detailed explanation of AP-SoC Zynq 7000 Architecture

Zynq 7000 AP SoC ,as shown in Figure given below, mainly consists of two parts: Processor System(PS), Programmable Logic(PL). PS literally employs to implement software functions of a hybrid system while hardware related functions are realized in PL. The PS part in Zynq 7000 is further composed of Application Processor Unit (APU), Memory interfaces, Central interconnects, Input Output Peripherals (IOPs), and Multiplexed IO (MIO). APU is the central part of the PS which controls and regulates all parts of PS.APU can have either single CPU or dual CPU. Two independent L1 D cache and I cache are, respectively, employed for data and instructions in each CPU. Snoop Control Unit (SCU) are exploited to maintain the coherency between L1 caches of both processor. Coherency ensures that caches in the respective CPU have updated data. L2 caches further act as bridge between L1 cache and DDR ram. DDR ram are relatively bigger memory (e.g. 512MB in Zedboard). Besides L1, L2, and DDR ram, there is 256KB On Chip Memory (OCM) which can be used for the application which requires low latency. Watch Dog Timers (AWDT, SWDT) are utilized to reset the PS when it malfunctions.

Additionally, Timers (private timer, TTC) can be employed as timer or counter.  There are 8 Direct Memory Access (DMA) in PS as well which also plays considerable role in improving the performance of the PS. The key feature of MMU is the address translation. It translates addresses of code and data from the virtual view of memory to the physical addresses in the real system. It enables tasks or applications to be written in a way which requires them to have no knowledge of the physical memory map of the system, or about other programs which might be running at the same time. This makes programming of applications much simpler, as it enables to use the same virtual memory address space for each.
5

The generic interrupt controller (GIC) is a centralized resource for managing interrupts sent to the CPUs from the PS and PL. The controller enables, disables, masks, and prioritizes the interrupt sources and sends them to the selected CPU (or CPUs) in a programmed manner as the CPU interface accepts the next interrupt. Central interconnect acts as a bridge between IOP, memory interfaces, memory interfaces, and General port (GP). As shown in the Figure 1 that there many IOP controllers in PS. The I/O Peripherals (IOP) are a collection of industry-standard interfaces for external data Communication. IOP controller can access both OCM and DDR ram via central interconnects. IOPs can be accessed via 54 pins MIO which are dynamically shared among different IOPs.

In Zynq 7000 SoC, The PS and PL can be tightly or loosely coupled using multiple interfaces and other signals that have a combined total of over 3,000 connections. This enables user to effectively integrate user-created hardware accelerators and other functions in the PL logic that are accessible to the processors and can also access memory resources in the processing system. The PS and the PL are on separate power domains, enabling the user to design power efficient design. Extended MIO (EMIO), GP, High Performance (HP) ports, and accelerator coherency port (ACP) enable the users to connect the PL with PS for variety of applications. IOPs of PS can be passed to PL via EMIO. GP are low data rate interface which are mainly used to configure the custom accelerators in PL part. HP port are used for data flow. HP port can access OCM and DDR ram respectively, for low latency and relatively larger data storage. ACP has even lower latency than HP and like HP it can access OCM and DDR depending upon the application. Any kind of logic can be implemented in PL part of SoC. It has 12 ADC as well. Programmable IO enables PL to talk with the external world. The Zynq-7000 AP SoC can be booted securely or non-securely. The PL configuration bitstream can be applied securely or non-securely. Both of these use the 256b AES decryption and SHA authentication blocks that are part of the PL. Therefore, to use these security features, the PL must be powered on.

AP SoC (Zynq 7000) Hybrid Hardware Architecture Basics

In this series of tutorial I planned to explain the Zynq 7000 architecture in details. The series is divided into three parts:

  • Firstly,  the peripheral interfaces of processor and FPGA will be explained and implemented in vivado.
  • Secondly, AXI interfaces (AXI4, AXI-Stream, and AXI-lite) will be demonstrated.
  • Lastly, Advance features of Zynq 7000 architecture will be realized e.g performance measurements of DMA , OCM, DDR etc.

I, however, find it better to briefly explain the basic concepts that shall be used later in this series.

 hybrid hardware architecture

Nowadays hybrid hardware architecture (HHA) is increasingly being used in embedded systems (ES). A typical ES has processor, memory unit and inputs/outputs (IOs). Processor is the brain that control the entire ES. Memory supports the processor by holding data temporarily or permanently. IOs are used to interact with external world. Sometimes single processor is not enough to meet all requirements. Therefore some other devices such as FPGA or application specific integrated circuit (ASIC) are embedded with processor to meet the given requirements. This kind of architecture is called hybrid architecture. The typical example of HHA is shown in the following Figure. A typical example of this architecture can be seen in ZYNQ 7000 series.

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System on Chip

In System on Chip (SoC) the electronic components are integrated on a single chip. The components can be analog, digital or mixed signals. Xilinx has introduced a new realm called All Programmable SOC (AP-SoC). In AP-SOC software programmability of a processor and the hardware programmability of an FPGA are integrated in a single chip. A typical example of this architecture can be seen in ZYNQ 7000 series.

In the following series of tutorial I will use ZEDBOARD which is an evaluation board with ZYNQ 7000 AP-SOC together many integrated peripherals.

How an FPGA Works

Before diving into ZEDBOARD, reader should have some basics about how an FPGA works. Assuming reader already knows about processor, I have given a general overview of an FPGA in the following few paragraphs. In this module, an effort is made to explain the general architecture of a FPGA.  A top down approach (from general to specific) is employed in this tutorial.

“A picture is worth a thousand words”   as stated by Fred, therefore we added as many pictures as possible to explain the concepts in easiest way. Following Figure shows the simplest form of an FPGA architecture. It is worth to note that real FPGA are much more complex than this. However, more or less, basic components remains same in all FPGA architectures. An FPGA has mainly three parts: CLB (Configurable Logic Block), routing channel, and IO (Input Output) Bank.

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CLB are reprogrammable blocks used to implement any kind of logic. Routing channel enables different CLB to communicate with each other and IO bank connect the FPGA with the outer world. New FPGAs have more components like DSP block, but these components are not discussed in this tutorial. Lets goes a bit further to FPGA architecture. Each CLB consists of more than one Slices. Group of LUTs(Look Up Table) and flip-flops constitutes Slices. The Figure ,given below, illustrates the relationship between CLBs and LUTs.

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LUTs are basically RAMs. Any kind of logic can be implemented by exploiting LUT. Let’s explain this concept by an example. For example, if we want to implement OR gate the contents of the RAM would be like this.

Address_Index(in[1:0])

Out

00

0
01

1

10

1

11

1

The LUT2 illustrated in following figure outputs based on address_index.

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To make long story short, nny kind of complex logic can be implemented by exploiting the LUTs. Of course, more the complex architecture is, more the required LUTs will be.

In the next lecture, The Zynq-7000 family architecture which is based on the All Programmable SoC architecture will be demonstrated. Furthermore, complete plan about when and which part of the AP SoC will be demonstrated. It is worth to note that I will use Zedboard (an evaluation board based on Zynq-7000 architecture) will be used throughout the lectures.