Detailed explanation of AP-SoC Zynq 7000 Architecture

Zynq 7000 AP SoC ,as shown in Figure given below, mainly consists of two parts: Processor System(PS), Programmable Logic(PL). PS literally employs to implement software functions of a hybrid system while hardware related functions are realized in PL. The PS part in Zynq 7000 is further composed of Application Processor Unit (APU), Memory interfaces, Central interconnects, Input Output Peripherals (IOPs), and Multiplexed IO (MIO). APU is the central part of the PS which controls and regulates all parts of PS.APU can have either single CPU or dual CPU. Two independent L1 D cache and I cache are, respectively, employed for data and instructions in each CPU. Snoop Control Unit (SCU) are exploited to maintain the coherency between L1 caches of both processor. Coherency ensures that caches in the respective CPU have updated data. L2 caches further act as bridge between L1 cache and DDR ram. DDR ram are relatively bigger memory (e.g. 512MB in Zedboard). Besides L1, L2, and DDR ram, there is 256KB On Chip Memory (OCM) which can be used for the application which requires low latency. Watch Dog Timers (AWDT, SWDT) are utilized to reset the PS when it malfunctions.

Additionally, Timers (private timer, TTC) can be employed as timer or counter.  There are 8 Direct Memory Access (DMA) in PS as well which also plays considerable role in improving the performance of the PS. The key feature of MMU is the address translation. It translates addresses of code and data from the virtual view of memory to the physical addresses in the real system. It enables tasks or applications to be written in a way which requires them to have no knowledge of the physical memory map of the system, or about other programs which might be running at the same time. This makes programming of applications much simpler, as it enables to use the same virtual memory address space for each.
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The generic interrupt controller (GIC) is a centralized resource for managing interrupts sent to the CPUs from the PS and PL. The controller enables, disables, masks, and prioritizes the interrupt sources and sends them to the selected CPU (or CPUs) in a programmed manner as the CPU interface accepts the next interrupt. Central interconnect acts as a bridge between IOP, memory interfaces, memory interfaces, and General port (GP). As shown in the Figure 1 that there many IOP controllers in PS. The I/O Peripherals (IOP) are a collection of industry-standard interfaces for external data Communication. IOP controller can access both OCM and DDR ram via central interconnects. IOPs can be accessed via 54 pins MIO which are dynamically shared among different IOPs.

In Zynq 7000 SoC, The PS and PL can be tightly or loosely coupled using multiple interfaces and other signals that have a combined total of over 3,000 connections. This enables user to effectively integrate user-created hardware accelerators and other functions in the PL logic that are accessible to the processors and can also access memory resources in the processing system. The PS and the PL are on separate power domains, enabling the user to design power efficient design. Extended MIO (EMIO), GP, High Performance (HP) ports, and accelerator coherency port (ACP) enable the users to connect the PL with PS for variety of applications. IOPs of PS can be passed to PL via EMIO. GP are low data rate interface which are mainly used to configure the custom accelerators in PL part. HP port are used for data flow. HP port can access OCM and DDR ram respectively, for low latency and relatively larger data storage. ACP has even lower latency than HP and like HP it can access OCM and DDR depending upon the application. Any kind of logic can be implemented in PL part of SoC. It has 12 ADC as well. Programmable IO enables PL to talk with the external world. The Zynq-7000 AP SoC can be booted securely or non-securely. The PL configuration bitstream can be applied securely or non-securely. Both of these use the 256b AES decryption and SHA authentication blocks that are part of the PL. Therefore, to use these security features, the PL must be powered on.

AP SoC (Zynq 7000) Hybrid Hardware Architecture Basics

In this series of tutorial I planned to explain the Zynq 7000 architecture in details. The series is divided into three parts:

  • Firstly,  the peripheral interfaces of processor and FPGA will be explained and implemented in vivado.
  • Secondly, AXI interfaces (AXI4, AXI-Stream, and AXI-lite) will be demonstrated.
  • Lastly, Advance features of Zynq 7000 architecture will be realized e.g performance measurements of DMA , OCM, DDR etc.

I, however, find it better to briefly explain the basic concepts that shall be used later in this series.

 hybrid hardware architecture

Nowadays hybrid hardware architecture (HHA) is increasingly being used in embedded systems (ES). A typical ES has processor, memory unit and inputs/outputs (IOs). Processor is the brain that control the entire ES. Memory supports the processor by holding data temporarily or permanently. IOs are used to interact with external world. Sometimes single processor is not enough to meet all requirements. Therefore some other devices such as FPGA or application specific integrated circuit (ASIC) are embedded with processor to meet the given requirements. This kind of architecture is called hybrid architecture. The typical example of HHA is shown in the following Figure. A typical example of this architecture can be seen in ZYNQ 7000 series.

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System on Chip

In System on Chip (SoC) the electronic components are integrated on a single chip. The components can be analog, digital or mixed signals. Xilinx has introduced a new realm called All Programmable SOC (AP-SoC). In AP-SOC software programmability of a processor and the hardware programmability of an FPGA are integrated in a single chip. A typical example of this architecture can be seen in ZYNQ 7000 series.

In the following series of tutorial I will use ZEDBOARD which is an evaluation board with ZYNQ 7000 AP-SOC together many integrated peripherals.

How an FPGA Works

Before diving into ZEDBOARD, reader should have some basics about how an FPGA works. Assuming reader already knows about processor, I have given a general overview of an FPGA in the following few paragraphs. In this module, an effort is made to explain the general architecture of a FPGA.  A top down approach (from general to specific) is employed in this tutorial.

“A picture is worth a thousand words”   as stated by Fred, therefore we added as many pictures as possible to explain the concepts in easiest way. Following Figure shows the simplest form of an FPGA architecture. It is worth to note that real FPGA are much more complex than this. However, more or less, basic components remains same in all FPGA architectures. An FPGA has mainly three parts: CLB (Configurable Logic Block), routing channel, and IO (Input Output) Bank.

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CLB are reprogrammable blocks used to implement any kind of logic. Routing channel enables different CLB to communicate with each other and IO bank connect the FPGA with the outer world. New FPGAs have more components like DSP block, but these components are not discussed in this tutorial. Lets goes a bit further to FPGA architecture. Each CLB consists of more than one Slices. Group of LUTs(Look Up Table) and flip-flops constitutes Slices. The Figure ,given below, illustrates the relationship between CLBs and LUTs.

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LUTs are basically RAMs. Any kind of logic can be implemented by exploiting LUT. Let’s explain this concept by an example. For example, if we want to implement OR gate the contents of the RAM would be like this.

Address_Index(in[1:0])

Out

00

0
01

1

10

1

11

1

The LUT2 illustrated in following figure outputs based on address_index.

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To make long story short, nny kind of complex logic can be implemented by exploiting the LUTs. Of course, more the complex architecture is, more the required LUTs will be.

In the next lecture, The Zynq-7000 family architecture which is based on the All Programmable SoC architecture will be demonstrated. Furthermore, complete plan about when and which part of the AP SoC will be demonstrated. It is worth to note that I will use Zedboard (an evaluation board based on Zynq-7000 architecture) will be used throughout the lectures.