Installation of Petalinux and running the first Petalinux based linux system on QEMU

Summary: This short tutorial, first, defines the petalinux, board support packages (BSP) and quick emulator (QEMU) used in zynq 7000 linux programming. It, secondly, describes the steps necessary to install petalinux on Ubuntu PC. Finally, an example on how to run and test the petalinux based linux system in QEMU is demonstrated.

1.  Definitions of Petalinux, BSP and QEMU: Petalinux, which is based on the yocto project, is a  Xilinx development toolchain which provides us everything necessary to build, test, customize and deploy an embedded linux system. Furthermore, it is an embedded linux distro maintained by Xilinx and targets Xilinx System on Chip (SoC) designs. It also has an integrated full system quick emulator (QEMU).  Developers can test and verify the customized linux solution on QEMU before deploying it on the actual hardware. Additionally, Xilnix also provides Board Support packages (BSP) for various Xilinx evaluation boards. A BSP describes the various hardware features supported by the corresponding evaluation board. Petalinux uses these BSPs to configure the kernel as per specification defined in them.    Read more

Detailed explanation of AP-SoC Zynq 7000 Architecture

Zynq 7000 AP SoC ,as shown in Figure given below, mainly consists of two parts: Processor System(PS), Programmable Logic(PL). PS literally employs to implement software functions of a hybrid system while hardware related functions are realized in PL. The PS part in Zynq 7000 is further composed of Application Processor Unit (APU), Memory interfaces, Central interconnects, Input Output Peripherals (IOPs), and Multiplexed IO (MIO). APU is the central part of the PS which controls and regulates all parts of PS.APU can have either single CPU or dual CPU. Two independent L1 D cache and I cache are, respectively, employed for data and instructions in each CPU. Snoop Control Unit (SCU) are exploited to maintain the coherency between L1 caches of both processor. Coherency ensures that caches in the respective CPU have updated data. L2 caches further act as bridge between L1 cache and DDR ram. DDR ram are relatively bigger memory (e.g. 512MB in Zedboard). Besides L1, L2, and DDR ram, there is 256KB On Chip Memory (OCM) which can be used for the application which requires low latency. Watch Dog Timers (AWDT, SWDT) are utilized to reset the PS when it malfunctions.

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AP SoC (Zynq 7000) Hybrid Hardware Architecture Basics

In this series of tutorial I planned to explain the Zynq 7000 architecture in details. The series is divided into three parts:

  • Firstly,  the peripheral interfaces of processor and FPGA will be explained and implemented in vivado.
  • Secondly, AXI interfaces (AXI4, AXI-Stream, and AXI-lite) will be demonstrated.
  • Lastly, Advance features of Zynq 7000 architecture will be realized e.g performance measurements of DMA , OCM, DDR etc.

I, however, find it better to briefly explain the basic concepts that shall be used later in this series. Read more